Package substrates, semiconductor packages having the package substrates, and methods for fabricating the semiconductor packages

ABSTRACT

Package substrates, semiconductor packages including the package substrates, and methods for fabricating the semiconductor packages are provided. A package substrate may include a core including a first surface on which a semiconductor chip is disposed and a second surface opposite the first surface. The package substrate may also include a metal pad on the second surface of the core. The metal pad may include a saline water corrosion resistant surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patentapplication Ser. No. 14/014,810, filed on Aug. 30, 2013, which claimspriority under 35 U.S.C. §119 to Korean Patent Application No.10-2012-0095594 filed on Aug. 30, 2012, the disclosures of which arehereby incorporated by reference in their entirety.

FIELD

The present disclosure generally relates to the field of electronics,and more particularly semiconductor packages.

BACKGROUND

In a Chip-on-board (COB) type package, a semiconductor chip is directlymounted on a printed circuit board. COB-type packages may be used in asmart card product and a semiconductor chip inserted in the smart cardproduct may have a contact with a card reader. Data may be read out fromor written to the semiconductor chip through the contact with the cardreader.

A COB-type package may include copper layers as circuits or electrodes.The copper layers may be plated with a layer including an expensivematerial such as, Au, Ni/Pd, or Ni/Au, to prevent the copper layers frombeing oxidized and to provide a surface for a wire bonding process.

SUMMARY

A semiconductor package may include a core including a first surface anda second surface opposite the first surface. The core may include athrough hole penetrating through the core. The semiconductor package mayalso include a metal pad on the first surface of the core and thethrough hole may expose a portion of the metal pad. The semiconductorpackage may further include a semiconductor chip on the second surfaceof the core and the metal pad may include a saline water corrosionresistant surface.

In various embodiments, the semiconductor package may include a bondingwire electrically connecting the semiconductor chip to the metal pad andthe bonding wire may pass through the through hole to connect to themetal pad.

In various embodiments, the semiconductor package may also include athrough via in the through hole and electrically connected to the metalpad, a chip pad on the second surface of the core and electricallyconnected to the through via, and a solder bump on the semiconductorchip. The solder bump may contact the chip pad, thereby thesemiconductor chip may be electrically connected to the metal pad

According to various embodiments, the metal pad may include aluminum,stainless steel, or brass.

In various embodiments, the saline water corrosion resistant surface mayinclude a surface film including chromium (Cr) and/or zirconium (Zr) onthe metal pad.

In various embodiments, the core may include glass epoxy or prepregmaterial.

In various embodiments, the semiconductor package may include anadhesion layer between the first surface of the core and the metal pad.

A method of fabricating a semiconductor package, the method may includeproviding a core including a first surface and a second surface oppositethe first surface, forming a through hole penetrating through the coreand forming a metal pad on the first surface of the core. The method mayalso include treating a surface of the metal pad to form a saline watercorrosion resistant surface. The method further include mounting asemiconductor chip on the second surface of the core and electricallyconnected to the metal pad and forming a molding layer on the secondsurface of the core encapsulating the semiconductor chip.

According to various embodiments, forming of the metal pad may includeattaching a metal foil on the first surface of the core and patterningthe metal foil to form the metal pad. The through hole may partiallyexpose a lower surface of the metal pad and the core may entirely exposean upper surface of the metal pad. The metal foil may include aluminum,stainless steel or brass

In various embodiments, the method may also include forming an adhesionlayer on the first surface of the core before the attaching of the metalfoil. The adhesion layer may extend between the first surface of thecore and the metal pad.

In various embodiments, the method may further include forming a bondingwire passing through the through hole and electrically connecting thesemiconductor chip to the metal pad.

According to various embodiments, the method may include forming athrough via including a conductive material in the through hole, forminga chip pad on the second surface of the core and electrically connectedto the through via, and forming a solder bump on the semiconductor chip.The through via may be electrically connected to the metal pad and thesolder bump may contact the chip pad, thereby the semiconductor chip maybe electrically connected to the metal pad.

In various embodiments, treating of the surface of the metal pad mayinclude treating the surface of the metal pad with chemical includingchromium (Cr) and/or zirconium (Zr).

According to various embodiments, the core may be mounted on a tapeextending along a direction and the semiconductor chip may be one of aplurality of semiconductor chips mounted on respective ones of aplurality of package substrates. The method may further include cuttingthe tape to separate the ones of plurality of package substrates fromone another.

A package substrate may include a core including a first surface onwhich a semiconductor chip is disposed and a second surface opposite thefirst surface. The package substrate may also include an aluminum pad onthe second surface of the core. The aluminum pad may include a salinewater corrosion resistant surface.

According to various embodiments, the saline water corrosion resistantsurface may include a surface film of chromium (Cr) and/or zirconium(Zr) on the aluminum pad.

In various embodiments, the core may include a through hole penetratingthrough the core and the through hole may expose a surface of thealuminum pad.

In various embodiments, the surface of the aluminum pad exposed by thethrough hole may include chromium (Cr) and/or zirconium (Zr).

A semiconductor package may include a package substrate including a coreincluding a through hole, an aluminum pad on a first surface of thecore, and an anti-corrosion layer on the aluminum pad. The semiconductorpackage may also include a semiconductor chip on a second surface of thecore opposite the first surface of the core and electrically connectedto the aluminum pad by a bonding wire. The bonding wire may pass throughthe through hole. The semiconductor package may further include amolding layer encapsulating the semiconductor chip and theanti-corrosion layer may have a corrosion resistance to saline water.

According to various embodiments, the anti-corrosion layer may include asurface film of chromium (Cr) and/or zirconium (Zr) on the aluminum pad.

An integrated circuit (IC) package substrate may include a package coreincluding an opening penetrating through the package core and aconductive pad on the package core. The opening may expose a portion ofthe conductive pad. The IC package may also include corrosion resistantlayers on surfaces of the conductive pad exposed by the package coreincluding the portion of the conductive pad exposed by the opening. Thecorrosion resistant layers may include chromium (Cr) or zirconium (Zr).

According to various embodiments, the conductive pad may includealuminum (Al).

In various embodiments, the conductive pad may include stainless steelor brass.

In various embodiments, the IC package may further include an adhesionlayer between the package core and the conductive pad. The opening maypenetrate through the adhesion layer to expose the portion of theconductive pad.

According to various embodiments, the package core may include apre-impregnate material.

In various embodiments, the conductive pad may contact the package core.

In various embodiments, a memory card may include the IC packagesubstrate and the memory card may further include a card body includinga cavity, in which the IC package substrate may be disposed. The memorycard may also include an integrated circuit on the package core and thepackage core may extend between the conductive pad and the integratedcircuit. The memory card may further include a conductive patternelectrically connecting the integrated circuit to the portion of theconductive pad. The conductive pad may include a first surface facingthe package core and a second surface opposite the first surface and thecard body may expose the second surface of the conductive pad.

In various embodiments, the conductive pattern may include a conductivewire including gold.

According to various embodiments, the integrated circuit may include asolder bump thereon and the conductive pattern may include a through viaand a chip pad. The through via may be in the opening and may contactthe portion of the conductive pad, and the chip pad may be on thepackage core and may electrically connect the through via to the solderbump.

In various embodiments, the memory card may include a mold layercovering the integrated circuit and the conductive pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 2A, 3A, 4A, and 5A are sectional views illustrating methods offabricating semiconductor packages according to some embodiments of theinventive concept.

FIGS. 1B, 2B, 3B, 4B, and 5B are plan views of FIGS. 1A, 2A, 3A, 4A, and5A, respectively.

FIG. 4C is a plan view illustrating of a semiconductor package accordingto some embodiments of the inventive concept.

FIGS. 6 and 7 are sectional views of semiconductor packages according tosome embodiments of the inventive concept.

FIG. 8 is a perspective view of a smart card including a semiconductorpackage according to some embodiments of the inventive concept.

DETAILED DESCRIPTION

Example embodiments of the inventive concepts are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments and intermediate structures ofexample embodiments. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments of theinventive concepts should not be construed as limited to the particularshapes illustrated herein but include deviations in shapes that result,for example, from manufacturing.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Example embodiments of the inventive concepts are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofexample embodiments. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments of theinventive concepts should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe actual shape of a region of a device and are not intended to limitthe scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments of theinventive concepts belong. It will be further understood that terms,such as those defined in commonly-used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

FIGS. 1A, 2A, 3A, 4A, and 5A are sectional views illustrating methods offabricating semiconductor packages according to some embodiments of theinventive concept. FIGS. 1B, 2B, 3B, 4B, and 5B are plan views of FIGS.1A, 2A, 3A, 4A, and 5A, respectively. FIG. 4C is a plan viewillustrating of a semiconductor package according to some embodiments ofthe inventive concept.

Referring to FIGS. 1A and 1B, a core 100 may be provided. The core 100may include a polymer layer (e.g., glass epoxy) having a first surface100 a and a second surface 100 b facing each other. An adhesion layer102 may be further formed on the first surface 100 a of the core 100.The core 100 may have a size corresponding to that of one semiconductorpackage and have a rectangular or square shape. Alternatively, the core100 may have a reel shape as shown in FIG. 4C, and thus, a plurality ofsemiconductor packages can be formed on the core 100.

Referring to FIGS. 2A and 2B, a plurality of through holes 104 may beformed to vertically penetrate the core 100. Each of the through holes104 may be shaped like a circle. In some embodiments, the through holes104 may be arranged in columns. In the case where the adhesion layer 102is additionally provided, the through holes 104 may be formed to furtherpenetrate the adhesion layer 102.

Referring to FIGS. 3A and 3B, an aluminum layer 121 may be attached ontothe first surface 100 a of the core 100. For example, the aluminum layer121 may be an aluminum foil that is attached on the adhesion layer 102and has a thickness less than that of the core 100. In some embodiments,the thickness of the aluminum layer 121 may be in a range of about ⅓ to⅔ of thickness of the core 100. For example, the core 100 may have athickness of about 100-120 μm (e.g., 110 μm), and the aluminum layer 121may have a thickness of about 40-80 μm (e.g., 70 μm). The adhesion layer102 may have a thickness of about 10-15 μm. An end portion of each ofthe through holes 104 may be closed by the aluminum layer 121, while theother end portion is open.

Referring to FIGS. 4A and 4B, the aluminum layer 121 may be patterned toform aluminum pads 120. The aluminum pads 120 may include a plurality ofpads 122, 124, and 126. For example, the aluminum pads 120 may include afirst pad 122, which extends from a central region of the core 100 toone of edges of the core 100 to have an “L” shape and is used totransmit a ground signal, second pads 124, which are provided at centralregions of both side regions of the core 100 and used to transmit datasignals, and third pads 126, each of which is provided at corners of thecore 100 to transmit a power signal and/or to serve as a dummy pad.However, embodiments of the inventive concepts may not be limited to theexemplified shape, purpose, and/or arrangement of the pads 122, 124, and126. A bottom surface of the aluminum pad 120 adjacent to the firstsurface 100 a of the core 100 may be partially exposed by the throughholes 104, and top and side surfaces thereof may be entirely exposed bythe core 100.

According to some embodiments of the inventive concept, a gold wire 144can be easily bonded to the aluminum pad 120. If the pad is formed ofnon-aluminum metal (e.g., copper), a plating layer (e.g., of Ni/Au orNi/Pd) on the copper pad may be formed for Au wire bonding. However, ifthe pad 120 is formed of aluminum, the process of forming the platinglayer may not be performed. In addition, a stable oxide layer (e.g.,Al₂O₃) may be formed on the aluminum pad 120 through a naturaloxidation, and thus a surface defect (e.g., surface bronzing) may bereduced.

In some embodiments, a surface layer 130 may be formed on the aluminumpad 120 by a surface treatment process. For example, the surfacetreatment process may include dipping the core 100 into solutioncontaining chromium (Cr), zirconium (Zr), or a mixture thereof orchemically treating a surface of the aluminum pad 120 usingelectroplating or electroless plating technology. The surface layer 130may be formed on the top and side surfaces of the aluminum pad 120 andon portions of the bottom surface of the aluminum pad 120 exposed by thethrough holes 104. In some embodiments, the surface layer 130 may beprovided in the form of film covering the surface of the aluminum pad120. Alternatively, the surface treatment may change the surface of thealuminum pad 120 into the surface layer 130 having high chemicalconcentration. As the result of the surface treatment process, thealuminum pad 120 can have an increased corrosion resistance to salinewater or NaCl.

Alternatively, after the formation of the aluminum layer 121 shown inFIG. 3A, the aluminum layer 121 may be chemically treated with chromium(Cr), zirconium (Zr), or a mixture thereof, and then, be patterned toform the aluminum pad 120.

The package substrate 1 may be formed to include the glass epoxy core100 and the aluminum pad 120 thereon. As shown in FIG. 4C, where thecore 100 is shaped like a reel, the core 100 may be separated to aplurality of the package substrates 1 by a slitting process. In someembodiments, the package substrate 1 may include a pad 120 containingstainless steel or brass instead of Al.

Referring to FIGS. 5A and 5B, a semiconductor chip 140 may be mounted onthe package substrate 1 and then a molding process may be performed. Forexample, the semiconductor chip 140 may be mounted on the second surface100 b of the core 100 and the gold wires 144 may be formed toelectrically connect the semiconductor chip 140 to the package substrate1. The gold wires 144 may connect to the aluminum pad 120 passingthrough the through holes 104. During the molding process, a moldinglayer 146 may be formed on the second surface 100 b of the core 100 toencapsulate the semiconductor chip 140, and as a result, a firstsemiconductor package 11 may be formed to have a chip-on-board (COB)structure.

FIGS. 6 and 7 are sectional views of semiconductor packages according tosome embodiments of the inventive concept.

Referring to FIG. 6, a second semiconductor package 12 may be configuredto have a chip-on-board (COB) structure. For example, in the secondsemiconductor package 12, the aluminum pad 120 may be provided on thefirst surface 100 a of the core 100 and the semiconductor chip 140 maybe mounted on the second surface 100 b of the core 100 and connect tothe package substrate 1 using a wire bonding. In some embodiments, thecore 100 may include at least one of pre-impregnated materials (orprepreg). The prepreg may exhibit an adhesive property in a B-stage (orhalf-cured state), unlike a C stage (or cured state) of the glass epoxy.Accordingly, there may be no need to form the adhesion layer 102 betweenthe core 100 and the aluminum pad 120 of the second semiconductorpackage 12.

Referring to FIG. 7, a third semiconductor package 13 may be configuredto have a flip-chip package structure, in which the semiconductor chip140 is mounted on the package substrate 1 in a flip-chip bonding manner.The semiconductor chip 140 may be mounted on the second surface 100 b ofthe core 100 in a face-down manner and electrically connects to thepackage substrate 1 via solder bumps 145. The package substrate 1 mayinclude a through via 152, which electrically connects to the aluminumpad 120 and penetrates the core 100, and a chip pad 154 electricallyconnecting the through via 152 to the solder bump 145. The chip pad 154may be redistributed. The aluminum pad 120 may be chemically treatedwith chromium (Cr), zirconium (Zr), or a mixture thereof, thereby havingan increased corrosion resistance to saline water or NaCl. Where thecore 100 includes glass epoxy, the adhesion layer 102 may be interposedbetween the core 100 and the aluminum pad 120. Where the core 100includes prepreg, the adhesion layer 102 may not be formed between thecore 100 and the aluminum pad 120.

FIG. 8 is a perspective view of a smart card including a semiconductorpackage according to some embodiments of the inventive concept.

Referring to FIG. 8, a smart card 500 may include a semiconductorpackage 10 and a card body 510. The card body 510 may include a cavity512 in which the semiconductor package 10 is inserted. The semiconductorpackage 10 may be one of the first to third semiconductor packages 11,12, and 13 described above. The semiconductor package 10 may be insertedinto the cavity 512 in such a way that the aluminum pad 120 is exposed.

According to some embodiments of the inventive concept, a pad and anelectrode of a package substrate may be formed of a foil made ofaluminum, stainless steel, or brass. A conventional plating process maynot be performed and thus a fabrication cost may be lowered. In someembodiments, since the pad of the package substrate is formed ofaluminum, and a wire bonding process can performed without a pad platingprocess and technical difficulties, such as surface bronzing, may bereduced. In addition, the pad of the package substrate may be chemicallytreated using chromium (Cr) or zirconium (Zr), thereby having anincreased corrosion resistance with respect to saline water and thuscorrosion of the package may be reduced and durability of the packagemay be improved.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the inventive concept. Thus, to the maximumextent allowed by law, the scope is to be determined by the broadestpermissible interpretation of the following claims and theirequivalents, and shall not be restricted or limited by the foregoingdetailed description.

What is claimed is:
 1. A method of fabricating a semiconductor package,the method comprising: providing a core comprising a first surface and asecond surface opposite the first surface; forming a through holepenetrating through the core; forming a metal pad on the first surfaceof the core; treating a surface of the metal pad to form a saline watercorrosion resistant surface; mounting a semiconductor chip on the secondsurface of the core and electrically connected to the metal pad; andforming a molding layer on the second surface of the core encapsulatingthe semiconductor chip.
 2. A semiconductor package comprising: a packagesubstrate comprising a core including a through hole, an aluminum pad ona first surface of the core, and an anti-corrosion layer on the aluminumpad; a semiconductor chip on a second surface of the core opposite thefirst surface of the core and electrically connected to the aluminum padby a bonding wire, the bonding wire passing through the through hole;and a molding layer encapsulating the semiconductor chip, wherein theanti-corrosion layer has a corrosion resistance to saline water.